With reference to FIGS. 1A and 1B, a standard DRAM utilizes a charge storage cell for storing a data bit which is comprised of a cell access FET 1 which has its gate connected to a word line 3 and its drain connected to a bit line 5. A capacitor, created using field effect technology, is connected between source of FET 1 and a voltage source, shown as V.sub.pp.
When such a charge storage cell is fabricated for DRAMs, special processing techniques are used to optimize its structure. However, when implementing an imbedded DRAM in an ASIC process, the special processing techniques and structures cannot be used.
Some of the techniques and structures that cannot be used in fabricating DRAMs in ASICs are as follows. DRAMs of 1 Mbits per chip and earlier used planar capacitors with special oxides and implants to maintain linearity over the full range of stored charge levels. DRAMs with densities of 4 Mbits per chip or greater make use of stacked capacitor or trench capacitor structures.
DRAM cells in standard DRAM chips reside either in an isolation well (e.g. using a triple well process), or in the chip substrate that has a back bias voltage applied. This structure protects the memory cells from disturbances caused by peripheral logic and input/output pin switching.
Cell access transistors in standard DRAM have well controlled subthreshold current from a combination of special implant and/or back bias. Extended refresh intervals can be achieved only if the subthreshold leakage is minimized.
In implementing DRAM cells in an ASIC, the structure and voltages illustrated in FIG. 1B can be used, which in many ways resembles a DRAM storage cell. The FET 1 is implemented as an n channel device having n doped diffused regions 7 in a p.sup.- doped substrate 8, and a conductive gate 9 above and insulated from the n channel. The capacitor 2 is an n channel device formed of a conductive plate 11 overlying the substrate 8 next to an n region 7. The bit line 5 carrying charge to be stored by the capacitor is connected to the other n region, and the word line 3, which carries voltage to enable the FET to transfer the charge carried by the bitline to the capacitor n channel, is connected to the gate of the FET. A voltage V.sub.ss is applied to the substrate 8.
However the plate 11 of the capacitor must be held at a high positive voltage V.sub.pp so that the n channel below it remains inverted even with a voltage of V.sub.dd stored by the capacitor, so that the capacitor behaves as a linear device. If it does not, the capacitance would vary as shown in FIG. 1C, where C.sub.OX is the capacitor capacitance, V.sub.GD and V.sub.GD are the gate to source or gate to drain voltage of the capacitor, and V.sub.T is the device threshold voltage. It is desirable to maintain C.sub.OX in the constant capacitance region of the curve.
Further, the wordline must be driven to the high positive voltage V.sub.pp, so that a full V.sub.dd voltage level can be written into the capacitor.
The above structure has found have problems when used in an ASIC process. For example, the p- doped substrate has V.sub.ss connected to it, not a back bias voltage V.sub.BB as used in memory processes. Undershoot noise from peripheral circuits or input output pins can inject minority carriers into the substrate, which can destroy stored data.
Further, since there is no back bias voltage on the memory cell access FET, subthreshold leakage from the capacitor is high, and as a result charge retention time by the cell is relatively low.
FIGS. 2A and 2B illustrate a schematic circuit and corresponding chip crossection of a storage cell which uses a p channel capacitor for storage of charge, and a p channel FET. In this case the memory cell is contained in an n- well 14, and is protected from peripheral circuitry by a V.sub.pp voltage biasing the n- region. The V.sub.pp voltage is applied to the n- region by means of an n doped region 16 contained in region 14.
The cell access FET is a p channel device having p doped regions 17 on opposite sides of its p channel, and a gate conductor 9 overlying the channel. The cell capacitor is formed of conductive plate 11 located with one edge adjacent one of the p regions 17. A negative voltage V.sub.BB is connected to the conductive plate 11.
With the n- well biased at a V.sub.pp higher than V.sub.dd, subthreshold leakage to the substrate 8 is inhibited. However the wordline 3, which is held at V.sub.dd voltage in the off state, must go negative to a voltage lower than V.sub.ss in order to fully turn on the cell access FET, and allow a full V.sub.ss voltage level to be stored by the cell. The gate (conductive plate 11) of the capacitor must be held at the negative V.sub.BB level to maintain an inverted channel below it, even when a zero (V.sub.ss) is stored.
However, the voltage V.sub.BB cannot be generated in normal CMOS circuits since the p.sup.- substrate 8 is connected to V.sub.ss. A negative voltage cannot be connected to any n- channel source or drain because it would forward bias to the substrate. P- channel dynamic circuits must be used to generate the V.sub.BB voltage and in the wordline driver.
Further, channel to n.sup.- well 14 leakage occurs, which affects retention of stored data.